The present invention relates generally to semiconductor manufacturing and, more particularly, to method and apparatus for implementing a universal coordinate system for metrology data.
Technology advancements in the manufacturing industry have resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (e.g., patterning, etching, doping, ion implanting, etc.), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using a patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for a transistor, a conductive line, or an isolation structure.
Designers place certain features at specific locations on each device to achieve the desired electrical function. These features are fabricated on to optical templates called “reticles”. Reticles are capable of producing a two dimensional pattern that can be printed onto a photosensitive surface using light of the appropriate wavelength. Many reticles contain a repeated pattern of the device laid out in a regular array. The space between each device pattern, sometimes referred to as a scribe line, is often used to place patterns of structures that aid in the test and measurement of the wafers produced. The image of the pattern on the reticle is produced on the wafer by shining light through each such multi-device reticle. This illumination process is often called a “flash”. Depending on the application, a single flash may encompass any desired number of individual die. Multiple flash or illumination processes are performed across the surface of the wafer so that all die on the wafer are subject to this process.
Three-dimensional features are obtained through an intricate sequence of steps that build a single two-dimensional layer at a time. The position of the features at each layer are different but are related to each other. Measurements and tests of different features on different flashes/dies are important to ascertaining the stability of the manufacturing process and its uniformity across each wafer 100.
FIG. 1 illustrates a wafer map of a typical semiconductor wafer 100. Each wafer 100 can accommodate a number of flashes (and by derivation, a number of devices) usually through a Cartesian grid layout 110 called a stepping pattern. In the illustrative embodiment depicted in FIG. 1, a so-called 3×2 flash pattern is depicted wherein six die are exposed in a single flash. Of course, as indicated above, the number of die in a single flash may vary depending upon the application. The equipment that subjects each wafer to this photolithographic process is called a stepper. The device that is formed on the surface of a wafer is called a die 120. A notch 130 is provided for aligning the wafer 100 in a particular tool. Other features may be used for alignment, such as a flat edge portion.
Data is collected at various steps during the manufacturing process to ensure conformance to production standards. This data may include performance data, such as the yield of the wafer 100 (i.e., which die 120 are functional), the speed of each die 120, the power consumption of each die 120, etc. This data may also include metrology data relating the fabrication of the wafer, such as process layer thickness, critical dimensions, etc.
Finally, after the wafer processing is complete, the wafers 100 are diced into chips that are then encased inside plastic or ceramic packages with metal leads that can be used to attach the chips to other electrical circuits such as printed circuit assemblies. A complex mapping exists between the features that were fabricated into each chip and the signals provided at each metal lead. The mapping gets exercised each time electrical current is applied to specific leads. When a chip fails to perform its electrical function, the failure can mostly be attributed to this complex sequence of structures. Analyzing the cause for failures thus becomes an exercise in correlating data spatially. Further, since the physical confirmation of the failed structure can only be established through expensive analytical techniques like Atomic Force Microscopy, it is important to have a high degree of confidence in localizing the area of failure.
Hence, the metrology data collected on the wafer 100 has spatial significance. In other words, it is useful to know the location on the wafer 100 where the metrology data was collected. Various metrology tools use different coordinate systems for specifying location. For example, a rectangular coordinate system may be defined with a designated origin 140. For instance, the origin 140 may be located at the center of the wafer 100. Other coordinate systems may use an origin not located on the wafer 100 or at a different position on the wafer 100. Such coordinateness systems may be Cartesian or radial. Metrology tools from different manufacturers may have different coordinate systems.
The metrology recipe may also have an effect on the relationship between the coordinates provided by the metrology tool and the actual location on the wafer 100. Certain metrology tools are more efficient if they traverse a wafer 100 in a certain direction. To increase throughput, the wafer 100 is rotated to align the measurement sites with the preferred direction. The metrology tool outputs the measurement coordinates in units that are not dependent on the rotational position of the wafer 100. Hence, location data from two different wafers 100 positioned at different rotational positions does not correspond to the same physical locations of the respective wafers. Other metrology tools do not report coordinates at all, but rather, only a reading order with no reference to physical wafer locations.
The complexities of wafer fabrication introduce several challenges to the effective utilization of metrology data in a system with inconsistent coordinate systems. Due to the variation in coordinate systems employed, it is difficult to correlate metrology data to specific positions on a wafer. Hence, it is more difficult to identify yield issues and adjust the process to improve results. This slower response results in longer manufacturing ramp times and potentially decreased profitability.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.